Multi-processor Embedded System Simulation Based on Combination of SystemC and SCP

To make HW/SW co-simulation of multi-processor embedded systems(MPES) fast enough for real applications while keeping simulation reasonably accurate,a methodology based on combination of SystemC and a source code parser(SCP) is presented.The SCP tool was developed to transform embedded software source codes to ANSI C codes annotated with time information.By using a BFM(bus functional model), these codes can be integrated into the SystemC system model as time annotation(TA) models of an EPU (embedded processing unit).Special SystemC modules were developed for modeling HW.Synchronization mechanism of SystemC simulation kernel was also extended to support a new processor-centralized synchronous simulation.The TA model and new synchronization mechanism can both improve simulation performance effectively.By implementing this methodology,a communication equipment including 12 processors was modeled and simulated successfully.The time required to simulate the target equipment behavior of 1 s is 59.8s.Experiments verified this methodology can be applied to HW/SW co-design of MPES.