HOU Li-gang, LI Mo, XIE Tong, WU Wu-chen. H.264 Chip Power Grid Optimization by IO Cell Placement[J]. Journal of Beijing University of Technology, 2006, 32(10): 865-869.
Citation:
HOU Li-gang, LI Mo, XIE Tong, WU Wu-chen. H.264 Chip Power Grid Optimization by IO Cell Placement[J]. Journal of Beijing University of Technology, 2006, 32(10): 865-869.
HOU Li-gang, LI Mo, XIE Tong, WU Wu-chen. H.264 Chip Power Grid Optimization by IO Cell Placement[J]. Journal of Beijing University of Technology, 2006, 32(10): 865-869.
Citation:
HOU Li-gang, LI Mo, XIE Tong, WU Wu-chen. H.264 Chip Power Grid Optimization by IO Cell Placement[J]. Journal of Beijing University of Technology, 2006, 32(10): 865-869.
H.264 Chip Power Grid Optimization by IO Cell Placement
To optimize the power grid design of a H.264 video decoder chip,the authors put forward the novel algorithm on an auto I/O cell placement(IOAP).The corresponding software is developed,and the experiment is done.The result of H.264 video decoder chip is obvious,and 7.22% of the total length and 16.57% of the routing time is saved.The whole chip's performance and design convergence has been improved.
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