Method to Reduce the Complexity of MIMO Receiver in B3G System

WANG Qiang; TAO Xiao-feng; XU Ling-jun; SHU Jing; ZHANG Ping

doi:10.3969/j.issn.0254-0037.2008.10.005

Journal of Beijing University of Technology > 2008 > 34(10): 1032-1037. > DOI: 10.3969/j.issn.0254-0037.2008.10.005

WANG Qiang, TAO Xiao-feng, XU Ling-jun, SHU Jing, ZHANG Ping. Method to Reduce the Complexity of MIMO Receiver in B3G System[J]. Journal of Beijing University of Technology, 2008, 34(10): 1032-1037. DOI: 10.3969/j.issn.0254-0037.2008.10.005

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Method to Reduce the Complexity of MIMO Receiver in B3G System

Wireless Technology Innovation Institute, Beijing University of Posts and Telecommunications, Beijing 100876, China

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Received Date: April 10, 2007
Available Online: December 17, 2022

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To reduce the resources of MIMO receiver during FPGA implement,this paper simplifies the V- BLAST (Vertical Bell lab Layered Spaced-Time) detection algorithm,applies bit-width reduction technique to save resources,and uses fixed point logic to keep the performance.Simulation shows that the BER (Bit Error Rate) performance is close to Golden detection algorithm,but the complexity is greatly less.Statistics on resource occupation of such schemes in VertexⅡ-Pro Series FPGA of Xilinx Company was given,while the schemes were verified on B3G TDD system hardware platform.The result shows that the simplified implementation schemes are applicable to hardware implementation of B3G TDD system MIMO receiver.
- receiver,
- orthogonal frequency-division,
- field programmable gate arrays

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