H.264 Chip Power Grid Optimization by IO Cell Placement

HOU Li-gang; LI Mo; XIE Tong; WU Wu-chen

doi:10.3969/j.issn.0254-0037.2006.10.001

Journal of Beijing University of Technology > 2006 > 32(10): 865-869. > DOI: 10.3969/j.issn.0254-0037.2006.10.001

HOU Li-gang, LI Mo, XIE Tong, WU Wu-chen. H.264 Chip Power Grid Optimization by IO Cell Placement[J]. Journal of Beijing University of Technology, 2006, 32(10): 865-869. DOI: 10.3969/j.issn.0254-0037.2006.10.001

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H.264 Chip Power Grid Optimization by IO Cell Placement

VLSI & System Lab, Beijing University of Technology, Beijing 100022, China

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Received Date: October 20, 2005
Available Online: December 29, 2022

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To optimize the power grid design of a H.264 video decoder chip,the authors put forward the novel algorithm on an auto I/O cell placement(IOAP).The corresponding software is developed,and the experiment is done.The result of H.264 video decoder chip is obvious,and 7.22% of the total length and 16.57% of the routing time is saved.The whole chip's performance and design convergence has been improved.
- power supply,
- automatic placement,
- electronic design automation(EDA)

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