Simulation of Intra-gate Resistive Bridging Faults in VLSI Based on IDDQ Testing

To realistically simulate the bridging faults in VLSI and to evaluate the quality of the test set,an intra-gate non-zero resistance bridging fault simulation algorithm based on IDDQ testing was proposed.First,a fault coverage criteria was proposed for this type of fault. Second,the fault dictionary for every type of the primitive logic gate cells was constructed by using the circuit-level fault injection and simulation method. Lastly, the gate-level fault simulation was accomplished by querying the fault dictionary when performing the functional simulation of the target logic circuit. Experimental results show that,comparing with the traditional approach,the proposed method in this paper can better reflect the fault covering ability of the test set against the realistic bridging faults and the simulation is efficient.