Abstract: In order to raise parallelism of executing instructions by model machine,this paper introduces the schema of designing a pipeline model machine.Using Verilog HDL,a pipeline model machine with parallelism of instructions which is combined with top-down method and DFA is implemented.This paper describes the schema and some algorithms of the pipeline model machine and simulates this machine in the end.The simula- tion results show that the model machine can process 4 instructions at the same time,and has the per-for- mances of pre-fetching instructions and bypassing.