Abstract: An aluminum gate 100-element CCD analog delay line has been fabricated using a lift-off technique employing an auxiliary poly-Si layer. Experiment testifies that this technique can readily obtain high finished productivity in the metallization of large scale integration where small conductor linewidths and small spaces (less than 2.5 μm) between conductors are reguired. The poly-Si layer between transfer electrodes serves as a excellent passivation. The design of diffusion tunnels for interconnections in the 3-phase structure has been improved.