Abstract: To reduce the resources of MIMO receiver during FPGA implement,this paper simplifies the V- BLAST (Vertical Bell lab Layered Spaced-Time) detection algorithm,applies bit-width reduction technique to save resources,and uses fixed point logic to keep the performance.Simulation shows that the BER (Bit Error Rate) performance is close to Golden detection algorithm,but the complexity is greatly less.Statistics on resource occupation of such schemes in VertexⅡ-Pro Series FPGA of Xilinx Company was given,while the schemes were verified on B3G TDD system hardware platform.The result shows that the simplified implementation schemes are applicable to hardware implementation of B3G TDD system MIMO receiver.