基于VHDL的有限状态机设计

Design of Finite State Machine Based on VHDL

摘要: 通过2种状态机的设计方法比较,说明使用VHDL语言设计出稳定、可靠的有限状态机的方法是有效的和实用的.由于两者对状态寄存器值的不同处理方法,使得状态机在采用不同编码方法时可靠性出现差异.针对此问题提出的状态机设计方法很好的解决了这个问题,保证采用常用编码方法进行状态机编码时,不管采用何种状态机的设计方法,状态机都会处于稳定、可靠状态.

Abstract: Comparing two finite state machine, declare how to use VHDL to design a reliable and stable finite state machine. Due to the difference between the two finite state machine, then their stability is different with new method proposed in this paper, we can design a reliable and stable finite state machine when take normal code method.