朱慧, 孙烨镕, 李屹林, 姚智文, 张轶群, 张之壤, 刘行. 不同工艺条件对柔性低温多晶硅薄膜晶体管性能影响[J]. 北京工业大学学报, 2024, 50(8): 914-920. DOI: 10.11936/bjutxb2022120021
    引用本文: 朱慧, 孙烨镕, 李屹林, 姚智文, 张轶群, 张之壤, 刘行. 不同工艺条件对柔性低温多晶硅薄膜晶体管性能影响[J]. 北京工业大学学报, 2024, 50(8): 914-920. DOI: 10.11936/bjutxb2022120021
    ZHU Hui, SUN Yerong, LI Yilin, YAO Zhiwen, ZHANG Yiqun, ZHANG Zhirang, LIU Xing. Influence of Different Process Conditions on the Performance of Flexible Low Temperature Polysilicon Thin Film Transistors[J]. Journal of Beijing University of Technology, 2024, 50(8): 914-920. DOI: 10.11936/bjutxb2022120021
    Citation: ZHU Hui, SUN Yerong, LI Yilin, YAO Zhiwen, ZHANG Yiqun, ZHANG Zhirang, LIU Xing. Influence of Different Process Conditions on the Performance of Flexible Low Temperature Polysilicon Thin Film Transistors[J]. Journal of Beijing University of Technology, 2024, 50(8): 914-920. DOI: 10.11936/bjutxb2022120021

    不同工艺条件对柔性低温多晶硅薄膜晶体管性能影响

    Influence of Different Process Conditions on the Performance of Flexible Low Temperature Polysilicon Thin Film Transistors

    • 摘要: 为了探究不同工艺对柔性低温多晶硅薄膜晶体管性能的影响, 对比了3种不同工艺薄膜晶体管的电学特性和陷阱特性。首先, 通过瞬态电流法研究陷阱, 运用陷阱对载流子的捕获和释放的特点测量得到瞬态电流曲线, 通过分别改变栅压和漏压并结合不同温度的陷阱去俘获峰值曲线提取的激活能分析得到不同俘获过程所对应的不同位置的3种陷阱。其次, 用仪器测量器件的I-V特性曲线, 提取器件的阈值电压VTH、亚阈值摆幅S和迁移率μ进行比对分析。结果显示, 样品A2的工艺改善了膜质, 降低了器件的阈值电压和关态漏电流, 同时降低了栅氧化层的陷阱密度; 样品A4的工艺填补了界面和沟道内的悬挂键, 优化了器件的迁移率和亚阈值摆幅, 同时降低了界面和晶界的陷阱密度。

       

      Abstract: To explore the influence of different processes on the performance of flexible low temperature polysilicon thin film transistors, the electrical characteristics and trap characteristics of thin film transistors with three different processes were compared. First, it measured the I-V characteristic curve of the device with an instrument, and extracted the VTH, S, and μ of the device for comparison and analysis. Second, the trap was studied by the transient current method, and the transient current curve was obtained by measuring the trapping and releasing characteristics of the carrier, and the activation energy analysis obtained by changing the gate voltage and the drain voltage and combining the detrapping curve at different temperatures. Three traps at different locations were achieved corresponding to different capture processes. Results show that the process of sample A2 improves the film quality, reduces the threshold voltage and off-state leakage current of the device, and simultaneously reduces the trap concentration of the gate oxide layer; the process of sample A4 fills the dangling bonds in the interface and channel, optimizing device mobility and subthreshold swing, while reducing the trap concentration at interfaces and grain boundaries.

       

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